Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Page     1-1


				PAGE    60,132
				TITLE   INDEGDT - 386 XMA Emulator - Build Global Descriptor Table
				
				COMMENT #
				* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
				*                                                                             *
				* MODULE NAME     : INDEGDT                                                   *
				*                                                                             *
				*                                                                             *
				*                    5669-196 (C) COPYRIGHT 1988 Microsoft Corp.              *
				*                                                                             *
				* DESCRIPTIVE NAME: Build the Global Descriptor Table (GDT)                   *
				*                                                                             *
				* STATUS (LEVEL)  : Version (0) Level (1.0)                                   *
				*                                                                             *
				* FUNCTION        : Build the Global Descriptor Table (GDT) for the 80386     *
				*                   XMA emulator                                              *
				*                                                                             *
				* MODULE TYPE     : ASM                                                       *
				*                                                                             *
				* REGISTER USAGE  : 80386 Standard                                            *
				*                                                                             *
				* RESTRICTIONS    : None                                                      *
				*                                                                             *
				* DEPENDENCIES    : None                                                      *
				*                                                                             *
				* ENTRY POINT     : GDT_BLD                                                   *
				*                                                                             *
				* LINKAGE         : Called NEAR from INDEINI                                  *
				*                                                                             *
				* INPUT PARMS     : None                                                      *
				*                                                                             *
				* RETURN PARMS    : None                                                      *
				*                                                                             *
				* OTHER EFFECTS   : None                                                      *
				*                                                                             *
				* EXIT NORMAL     : Return to INDEINI                                         *
				*                                                                             *
				* EXIT ERROR      : None                                                      *
				*                                                                             *
				* EXTERNAL                                                                    *
				* REFERENCES      : None                                                      *
				*                                                                             *
				* SUB-ROUTINES    : SREG_2_24BITS - Convert the 16 bit value in AX to a 24    *
				*                                   bit value in DH and AX.                   *
				*                   ADDOFF - Add the 16 bit offset in AX to the 24 bit value  *
				*                            in DH and BX.                                    *
				*                                                                             *
				* MACROS          : DESCR_DEF  - Declare a descriptor entry                   *
				*                   DESCR_INIT - Initialize a descriptor                      *
				*                                                                             *
				* CONTROL BLOCKS  : INDEDAT - System data structures                          *
				*                                                                             *
				* CHANGE ACTIVITY :                                                           *
				*                                                                             *
				* $MOD(INDEGDT) COMP(LOAD) PROD(3270PC) :                                     *
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
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				*                                                                             *
				* $D0=D0004700 410 870530 D : NEW FOR RELEASE 1.1                             *
				* $P1=P0000293 410 870731 D : LIMIT LINES TO 80 CHARACTERS                    *
				* $P2=P0000312 410 870804 D : CHANGE COMPONENT FROM MISC TO LOAD              *
				* $P3=P0000410 410 870918 D : RELOCATE DATA AREAS TO MAKE ROOM FOR BIT MAP    *
				*                                                                             *
				* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
				#
				
				        .286P                 ; Enable recognition of 286 privileged instructs.
				
				        .LIST                 ; Turn on the listing
				
 0000				PROG    SEGMENT PARA    PUBLIC  'PROG'
				
				        ASSUME  CS:PROG
				        ASSUME  SS:NOTHING
				        ASSUME  DS:PROG
				        ASSUME  ES:NOTHING
				
 0000				INDEGDT LABEL   NEAR
				
				        PUBLIC  INDEGDT
				        PUBLIC  GDT_BLD
				        PUBLIC  GDT_DATA_START
				        PUBLIC  SREG_2_24BITS
				
				;       The following data define a pre-initialized GDT.  They represent
				;       all structures which will exist when the emulator comes up.
				;       THESE MUST BE INITIALIZED IN THE ORDER IN WHICH THEY APPEAR IN THE
				;       GDT_DEF STRUCTURE DEFINITION AS IT APPEARS IN INDEDAT.INC.  This data
				;       area will be copied from the code segment to the final GDT resting
				;       place during initialization.
				
 0000				GDT_DATA_START  LABEL   WORD
				
				;               First entry is unusable
				
				       DESCR_DEF   SEG, 0, 0, 0, 0
 0000  0000                  1	        DW      0        ; Segment limit 
 0002  0000                  1	        DW      0        ; Segment base address - low word 
 0004  00                    1	        DB      0        ; Segment base address - high byte 
 0005  00                    1	        DB      0          ; Access rights byte 
 0006  0000                  1	        DW      0             ; Intel reserved 
				
				;               The descriptor for GDT itself
				
				       DESCR_DEF   SEG, GDT_LEN, GDT_LOC, 3, CPL0_DATA_ACCESS
 0008  1000                  1	        DW      GDT_LEN        ; Segment limit 
 000A  C100                  1	        DW      GDT_LOC        ; Segment base address - low word 
 000C  03                    1	        DB      3        ; Segment base address - high byte 
 000D  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 000E  0000                  1	        DW      0             ; Intel reserved 
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
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				PAGE
				
				;               The system IDT descriptor
				
				       DESCR_DEF   SEG, SIDT_LEN, SIDT_LOC, 3, CPL0_DATA_ACCESS
 0010  0800                  1	        DW      SIDT_LEN        ; Segment limit 
 0012  D100                  1	        DW      SIDT_LOC        ; Segment base address - low word 
 0014  03                    1	        DB      3        ; Segment base address - high byte 
 0015  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 0016  0000                  1	        DW      0             ; Intel reserved 
				
				;               The real system data area descriptor (XMA pages)
				
				       DESCR_DEF   SEG, 0FFFFH, 0000H, 11H, CPL0_DATA_ACCESS
 0018  FFFF                  1	        DW      0FFFFH        ; Segment limit 
 001A  0000                  1	        DW      0000H        ; Segment base address - low word 
 001C  11                    1	        DB      11H        ; Segment base address - high byte 
 001D  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 001E  0000                  1	        DW      0             ; Intel reserved 
				
				;               The virtual IDT descriptor  (not needed so use for all memory)
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, NSEG@_LO, NSEG@_HI, CPL0_DATA_ACCESS
 0020  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 0022  0000                  1	        DW      NSEG@_LO        ; Segment base address - low word 
 0024  00                    1	        DB      NSEG@_HI        ; Segment base address - high byte 
 0025  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 0026  0000                  1	        DW      0             ; Intel reserved 
				
				;               The LOADALL descriptor
				
				       DESCR_DEF   SEG, 0, 0, 0, 0
 0028  0000                  1	        DW      0        ; Segment limit 
 002A  0000                  1	        DW      0        ; Segment base address - low word 
 002C  00                    1	        DB      0        ; Segment base address - high byte 
 002D  00                    1	        DB      0          ; Access rights byte 
 002E  0000                  1	        DW      0             ; Intel reserved 
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
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				PAGE
				
				;               Compatible monochrome display
				
				       DESCR_DEF   SEG, MCRT_SIZE, MCRT@_LO, MCRT@_HI, CPL0_DATA_ACCESS
 0030  1000                  1	        DW      MCRT_SIZE        ; Segment limit 
 0032  0000                  1	        DW      MCRT@_LO        ; Segment base address - low word 
 0034  0B                    1	        DB      MCRT@_HI        ; Segment base address - high byte 
 0035  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 0036  0000                  1	        DW      0             ; Intel reserved 
				
				;               Compatible color display
				
				       DESCR_DEF   SEG, CCRT_SIZE, CCRT@_LO, CCRT@_HI, CPL0_DATA_ACCESS
 0038  4000                  1	        DW      CCRT_SIZE        ; Segment limit 
 003A  8000                  1	        DW      CCRT@_LO        ; Segment base address - low word 
 003C  0B                    1	        DB      CCRT@_HI        ; Segment base address - high byte 
 003D  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 003E  0000                  1	        DW      0             ; Intel reserved 
				
				;               Enhanced color display - one entry for each 64K              P1C
				
				       DESCR_DEF   SEG, ECCRT_SIZE, ECCRT@_LO_LO, ECCRT@_LO_HI, CPL0_DATA_ACCESS
 0040  FFFF                  1	        DW      ECCRT_SIZE        ; Segment limit 
 0042  0000                  1	        DW      ECCRT@_LO_LO        ; Segment base address - low word 
 0044  0A                    1	        DB      ECCRT@_LO_HI        ; Segment base address - high byte 
 0045  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 0046  0000                  1	        DW      0             ; Intel reserved 
				
				;               Second part of enhanced display                              P1C
				
				       DESCR_DEF   SEG, ECCRT_SIZE, ECCRT@_HI_LO, ECCRT@_HI_HI, CPL0_DATA_ACCESS
 0048  FFFF                  1	        DW      ECCRT_SIZE        ; Segment limit 
 004A  0000                  1	        DW      ECCRT@_HI_LO        ; Segment base address - low word 
 004C  0C                    1	        DB      ECCRT@_HI_HI        ; Segment base address - high byte 
 004D  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 004E  0000                  1	        DW      0             ; Intel reserved 
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
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				PAGE
				
				;               Code segment for ROM code, system IDT
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, CSEG@_LO, CSEG@_HI, CPL0_CODE_ACCESS
 0050  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 0052  0000                  1	        DW      CSEG@_LO        ; Segment base address - low word 
 0054  0E                    1	        DB      CSEG@_HI        ; Segment base address - high byte 
 0055  9B                    1	        DB      CPL0_CODE_ACCESS          ; Access rights byte 
 0056  0000                  1	        DW      0             ; Intel reserved 
				
				;               Data segment for ROM code, system IDT
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, CSEG@_LO, CSEG@_HI, CPL0_CODE_ACCESS
 0058  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 005A  0000                  1	        DW      CSEG@_LO        ; Segment base address - low word 
 005C  0E                    1	        DB      CSEG@_HI        ; Segment base address - high byte 
 005D  9B                    1	        DB      CPL0_CODE_ACCESS          ; Access rights byte 
 005E  0000                  1	        DW      0             ; Intel reserved 
				
				;               Temporarily, the monitor is installed using the patch
				;                segment descriptors in the GDT
				
 = 0000				MSEG@_LO        EQU     00000H
 = 0008				MSEG@_HI        EQU     008H
				
				
				;               Code segment for patch code, system IDT
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, MSEG@_LO, MSEG@_HI, CPL0_CODE_ACCESS
 0060  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 0062  0000                  1	        DW      MSEG@_LO        ; Segment base address - low word 
 0064  08                    1	        DB      MSEG@_HI        ; Segment base address - high byte 
 0065  9B                    1	        DB      CPL0_CODE_ACCESS          ; Access rights byte 
 0066  0000                  1	        DW      0             ; Intel reserved 
				
				;               Data segment for patch code, system IDT
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, MSEG@_LO, MSEG@_HI, CPL0_DATA_ACCESS
 0068  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 006A  0000                  1	        DW      MSEG@_LO        ; Segment base address - low word 
 006C  08                    1	        DB      MSEG@_HI        ; Segment base address - high byte 
 006D  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 006E  0000                  1	        DW      0             ; Intel reserved 
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
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				PAGE
				
				;               Code segment for ROM code, virtual IDT
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, CSEG@_LO, CSEG@_HI, CPL0_CODE_ACCESS
 0070  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 0072  0000                  1	        DW      CSEG@_LO        ; Segment base address - low word 
 0074  0E                    1	        DB      CSEG@_HI        ; Segment base address - high byte 
 0075  9B                    1	        DB      CPL0_CODE_ACCESS          ; Access rights byte 
 0076  0000                  1	        DW      0             ; Intel reserved 
				
				;               Data segment for ROM code, virtual IDT
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, CSEG@_LO, CSEG@_HI, CPL0_CODE_ACCESS
 0078  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 007A  0000                  1	        DW      CSEG@_LO        ; Segment base address - low word 
 007C  0E                    1	        DB      CSEG@_HI        ; Segment base address - high byte 
 007D  9B                    1	        DB      CPL0_CODE_ACCESS          ; Access rights byte 
 007E  0000                  1	        DW      0             ; Intel reserved 
				
				;               Code segment for patch code, virtual IDT
				
				       DESCR_DEF   SEG, NULL_SEG_LEN, NSEG@_LO, NSEG@_HI, NULL_ACCESS
 0080  0000                  1	        DW      NULL_SEG_LEN        ; Segment limit 
 0082  0000                  1	        DW      NSEG@_LO        ; Segment base address - low word 
 0084  00                    1	        DB      NSEG@_HI        ; Segment base address - high byte 
 0085  00                    1	        DB      NULL_ACCESS          ; Access rights byte 
 0086  0000                  1	        DW      0             ; Intel reserved 
				
				;               Data segment for patch code, virtual IDT
				
				       DESCR_DEF   SEG, NULL_SEG_LEN, NSEG@_LO, NSEG@_HI, NULL_ACCESS
 0088  0000                  1	        DW      NULL_SEG_LEN        ; Segment limit 
 008A  0000                  1	        DW      NSEG@_LO        ; Segment base address - low word 
 008C  00                    1	        DB      NSEG@_HI        ; Segment base address - high byte 
 008D  00                    1	        DB      NULL_ACCESS          ; Access rights byte 
 008E  0000                  1	        DW      0             ; Intel reserved 
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
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				PAGE
				
				;               Temporary descriptors for ES, CS, SS, and DS
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, NSEG@_LO, NSEG@_HI, CPL0_DATA_ACCESS
 0090  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 0092  0000                  1	        DW      NSEG@_LO        ; Segment base address - low word 
 0094  00                    1	        DB      NSEG@_HI        ; Segment base address - high byte 
 0095  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 0096  0000                  1	        DW      0             ; Intel reserved 
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, NSEG@_LO, NSEG@_HI, CPL0_CODE_ACCESS
 0098  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 009A  0000                  1	        DW      NSEG@_LO        ; Segment base address - low word 
 009C  00                    1	        DB      NSEG@_HI        ; Segment base address - high byte 
 009D  9B                    1	        DB      CPL0_CODE_ACCESS          ; Access rights byte 
 009E  0000                  1	        DW      0             ; Intel reserved 
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, NSEG@_LO, NSEG@_HI, CPL0_DATA_ACCESS
 00A0  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 00A2  0000                  1	        DW      NSEG@_LO        ; Segment base address - low word 
 00A4  00                    1	        DB      NSEG@_HI        ; Segment base address - high byte 
 00A5  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 00A6  0000                  1	        DW      0             ; Intel reserved 
				
				       DESCR_DEF   SEG, MAX_SEG_LEN, NSEG@_LO, NSEG@_HI, CPL0_DATA_ACCESS
 00A8  FFFF                  1	        DW      MAX_SEG_LEN        ; Segment limit 
 00AA  0000                  1	        DW      NSEG@_LO        ; Segment base address - low word 
 00AC  00                    1	        DB      NSEG@_HI        ; Segment base address - high byte 
 00AD  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 00AE  0000                  1	        DW      0             ; Intel reserved 
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
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				PAGE
				
				; These DQ's pad out the space between the last MultiPC descriptor and the
				; PMVM descriptors.  They don't need initialization.
				
 00B0  0009[			       DQ      9 DUP (0)     ; These 9 are for the Monitor descriptors
	   00000000000000	
	   00			
			 ]	
				
				
				;               This is for the keyboard owner (not used)
				
 00F8  0000000000000000		       DQ       0
				
				;               These 16 are for the virtual timer support
				
 0100  0010[			       DQ      16 DUP (0)
	   00000000000000	
	   00			
			 ]	
				
				
				; The following 32 descriptors are for exception condition task gates.
				
				       REPT    32
				       DQ       0
				       ENDM
 0180  0000000000000000      1	       DQ       0 
 0188  0000000000000000      1	       DQ       0 
 0190  0000000000000000      1	       DQ       0 
 0198  0000000000000000      1	       DQ       0 
 01A0  0000000000000000      1	       DQ       0 
 01A8  0000000000000000      1	       DQ       0 
 01B0  0000000000000000      1	       DQ       0 
 01B8  0000000000000000      1	       DQ       0 
 01C0  0000000000000000      1	       DQ       0 
 01C8  0000000000000000      1	       DQ       0 
 01D0  0000000000000000      1	       DQ       0 
 01D8  0000000000000000      1	       DQ       0 
 01E0  0000000000000000      1	       DQ       0 
 01E8  0000000000000000      1	       DQ       0 
 01F0  0000000000000000      1	       DQ       0 
 01F8  0000000000000000      1	       DQ       0 
 0200  0000000000000000      1	       DQ       0 
 0208  0000000000000000      1	       DQ       0 
 0210  0000000000000000      1	       DQ       0 
 0218  0000000000000000      1	       DQ       0 
 0220  0000000000000000      1	       DQ       0 
 0228  0000000000000000      1	       DQ       0 
 0230  0000000000000000      1	       DQ       0 
 0238  0000000000000000      1	       DQ       0 
 0240  0000000000000000      1	       DQ       0 
 0248  0000000000000000      1	       DQ       0 
 0250  0000000000000000      1	       DQ       0 
 0258  0000000000000000      1	       DQ       0 
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 0260  0000000000000000      1	       DQ       0 
 0268  0000000000000000      1	       DQ       0 
 0270  0000000000000000      1	       DQ       0 
 0278  0000000000000000      1	       DQ       0 
				
				; The following 16 pairs are for the hardware interrupt handling tasks.
				
				       REPT    16
				       DQ       0
				       DQ       0
				       ENDM
 0280  0000000000000000      1	       DQ       0 
 0288  0000000000000000      1	       DQ       0 
 0290  0000000000000000      1	       DQ       0 
 0298  0000000000000000      1	       DQ       0 
 02A0  0000000000000000      1	       DQ       0 
 02A8  0000000000000000      1	       DQ       0 
 02B0  0000000000000000      1	       DQ       0 
 02B8  0000000000000000      1	       DQ       0 
 02C0  0000000000000000      1	       DQ       0 
 02C8  0000000000000000      1	       DQ       0 
 02D0  0000000000000000      1	       DQ       0 
 02D8  0000000000000000      1	       DQ       0 
 02E0  0000000000000000      1	       DQ       0 
 02E8  0000000000000000      1	       DQ       0 
 02F0  0000000000000000      1	       DQ       0 
 02F8  0000000000000000      1	       DQ       0 
 0300  0000000000000000      1	       DQ       0 
 0308  0000000000000000      1	       DQ       0 
 0310  0000000000000000      1	       DQ       0 
 0318  0000000000000000      1	       DQ       0 
 0320  0000000000000000      1	       DQ       0 
 0328  0000000000000000      1	       DQ       0 
 0330  0000000000000000      1	       DQ       0 
 0338  0000000000000000      1	       DQ       0 
 0340  0000000000000000      1	       DQ       0 
 0348  0000000000000000      1	       DQ       0 
 0350  0000000000000000      1	       DQ       0 
 0358  0000000000000000      1	       DQ       0 
 0360  0000000000000000      1	       DQ       0 
 0368  0000000000000000      1	       DQ       0 
 0370  0000000000000000      1	       DQ       0 
 0378  0000000000000000      1	       DQ       0 
				
				; The following pair is for the DISPATCH task
				
				       DESCR_DEF   SEG, TSS_LEN, DISPATCH_LOC, 3, <TSS_ACCESS OR FREE_TSS>
 0380  2068                  1	        DW      TSS_LEN        ; Segment limit 
 0382  D900                  1	        DW      DISPATCH_LOC        ; Segment base address - low word 
 0384  03                    1	        DB      3        ; Segment base address - high byte 
 0385  81                    1	        DB      TSS_ACCESS OR FREE_TSS          ; Access rights byte 
 0386  0000                  1	        DW      0             ; Intel reserved 
				       DESCR_DEF   SEG, TSS_LEN, DISPATCH_LOC, 3, CPL0_DATA_ACCESS
 0388  2068                  1	        DW      TSS_LEN        ; Segment limit 
 038A  D900                  1	        DW      DISPATCH_LOC        ; Segment base address - low word 
 038C  03                    1	        DB      3        ; Segment base address - high byte 
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
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 038D  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 038E  0000                  1	        DW      0             ; Intel reserved 
				
				       DESCR_DEF   SEG, 0, 0, 0,LDT_DESC
 0390  0000                  1	        DW      0        ; Segment limit 
 0392  0000                  1	        DW      0        ; Segment base address - low word 
 0394  00                    1	        DB      0        ; Segment base address - high byte 
 0395  E2                    1	        DB      LDT_DESC          ; Access rights byte 
 0396  0000                  1	        DW      0             ; Intel reserved 
				
				; BASIC's segment
				
				       DESCR_DEF   SEG, 07FFFH, 06000H, 0FH, CPL0_DATA_ACCESS
 0398  7FFF                  1	        DW      07FFFH        ; Segment limit 
 039A  6000                  1	        DW      06000H        ; Segment base address - low word 
 039C  0F                    1	        DB      0FH        ; Segment base address - high byte 
 039D  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 039E  0000                  1	        DW      0             ; Intel reserved 
				
				; BIOS's segment
				
				       DESCR_DEF   SEG, 01FFFH, 00000H, 0FH, CPL0_DATA_ACCESS
 03A0  1FFF                  1	        DW      01FFFH        ; Segment limit 
 03A2  0000                  1	        DW      00000H        ; Segment base address - low word 
 03A4  0F                    1	        DB      0FH        ; Segment base address - high byte 
 03A5  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 03A6  0000                  1	        DW      0             ; Intel reserved 
				
 03A8  000D[			       DQ      13 DUP (0)      ; Reserved guys
	   00000000000000	
	   00			
			 ]	
				
				
				; The following guys are junk !  Used before the first TSS allocated. These
				;  have to be in the PMVM location in the GDT.
				
				       DESCR_DEF   SEG, TSS_LEN, 0C000H, 0, FREE_TSS         ; For the TR
 0410  2068                  1	        DW      TSS_LEN        ; Segment limit 
 0412  C000                  1	        DW      0C000H        ; Segment base address - low word 
 0414  00                    1	        DB      0        ; Segment base address - high byte 
 0415  81                    1	        DB      FREE_TSS          ; Access rights byte 
 0416  0000                  1	        DW      0             ; Intel reserved 
				
				       DESCR_DEF   SEG, TSS_LEN, 0C000H, 0, CPL0_DATA_ACCESS ; TSS as data
 0418  2068                  1	        DW      TSS_LEN        ; Segment limit 
 041A  C000                  1	        DW      0C000H        ; Segment base address - low word 
 041C  00                    1	        DB      0        ; Segment base address - high byte 
 041D  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 041E  0000                  1	        DW      0             ; Intel reserved 
				
				       DESCR_DEF   SEG, GDT_LEN, 0D000H, 0, LDT_DESC         ; For the LDTR
 0420  1000                  1	        DW      GDT_LEN        ; Segment limit 
 0422  D000                  1	        DW      0D000H        ; Segment base address - low word 
 0424  00                    1	        DB      0        ; Segment base address - high byte 
 0425  E2                    1	        DB      LDT_DESC          ; Access rights byte 
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
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 0426  0000                  1	        DW      0             ; Intel reserved 
				
				       DESCR_DEF   SEG, GDT_LEN, 0D000H, 0, CPL0_DATA_ACCESS ; LDT as data
 0428  1000                  1	        DW      GDT_LEN        ; Segment limit 
 042A  D000                  1	        DW      0D000H        ; Segment base address - low word 
 042C  00                    1	        DB      0        ; Segment base address - high byte 
 042D  93                    1	        DB      CPL0_DATA_ACCESS          ; Access rights byte 
 042E  0000                  1	        DW      0             ; Intel reserved 
				
 0430				GDT_DATA_END    LABEL   WORD
				
 = 0430				COPY_LEN        EQU     GDT_DATA_END-GDT_DATA_START
				
				;
				;       End of pre-allocated GDT
				;
				
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Page     1-12
                                                            

				PAGE
				
 0430				GDT_BLD         PROC    NEAR
				
				; Copy the pre-initialized GDT into its proper location in memory
				
 0430  FA			        CLI                             ; All string operations go forward
				
 0431  BE 0000 R		        MOV     SI,OFFSET GDT_DATA_START ; DS:SI points to the pre-initialized
				                                        ;   GDT above
 0434  B9 0218			        MOV     CX,COPY_LEN/2           ; CX = number of words to copy
 0437  BF C100			        MOV     DI,GDT_LOC              ; ES:DI points to the GDT location
 043A  F3/ A5			        REP     MOVSW                   ; Copy GDT into its final resting place
				
				; Now let's initialize some of the GDT entries
				
				; Set up the descriptors for our code segment and data segment
				
 043C  8C C8			        MOV     AX,CS                   ; Get our CS
 043E  E8 0545 R		        CALL    SREG_2_24BITS           ; And convert it to a 24 bit offset
 0441  8B D8			        MOV     BX,AX                   ; Get the monitor offset
				
 0443				ALLSET:
				        DESCR_INIT  SEG, SYS_PATCH_CS, 07FFFH, BX, DH, CPL0_CODE_ACCESS
 0443  50                    1	        PUSH    AX            ; Save the utility register 
 0444  BF 0060               1	        MOV     DI,SYS_PATCH_CS     ; Set up index value to proper descriptor 
 0447  81 C7 C100            1	        ADD     DI,GDT_LOC 
 044B  B8 7FFF               1	        MOV     AX,07FFFH       ; PARM1 = Segment Limit; load into AX 
 044E  AB                    1	        STOSW                   ;   and store 
 044F  8B C3                 1	        MOV     AX,BX       ; PARM2 = BASE_LO_W; load into AX 
 0451  AB                    1	        STOSW                   ;   and store 
 0452  8A C6                 1	        MOV     AL,DH       ; PARM3 = BASE_HI_B; load into AL, and 
 0454  B4 9B                 1	        MOV     AH,CPL0_CODE_ACCESS         ;   ARB = Access Rights Byte; load into AH 
 0456  AB                    1	        STOSW                   ;     and store both 
 0457  B8 0000               1	        MOV     AX,0            ; Make sure the Intel 
 045A  AB                    1	        STOSW                   ;   reserved word is zero 
 045B  58                    1	        POP     AX              ; Restore AX 
				        DESCR_INIT  SEG, SYS_PATCH_DS, 0FFFFH, BX, DH, CPL0_DATA_ACCESS
 045C  50                    1	        PUSH    AX            ; Save the utility register 
 045D  BF 0068               1	        MOV     DI,SYS_PATCH_DS     ; Set up index value to proper descriptor 
 0460  81 C7 C100            1	        ADD     DI,GDT_LOC 
 0464  B8 FFFF               1	        MOV     AX,0FFFFH       ; PARM1 = Segment Limit; load into AX 
 0467  AB                    1	        STOSW                   ;   and store 
 0468  8B C3                 1	        MOV     AX,BX       ; PARM2 = BASE_LO_W; load into AX 
 046A  AB                    1	        STOSW                   ;   and store 
 046B  8A C6                 1	        MOV     AL,DH       ; PARM3 = BASE_HI_B; load into AL, and 
 046D  B4 93                 1	        MOV     AH,CPL0_DATA_ACCESS         ;   ARB = Access Rights Byte; load into AH 
 046F  AB                    1	        STOSW                   ;     and store both 
 0470  B8 0000               1	        MOV     AX,0            ; Make sure the Intel 
 0473  AB                    1	        STOSW                   ;   reserved word is zero 
 0474  58                    1	        POP     AX              ; Restore AX 
				
				; Initialize the descriptor for the GDT
				
 0475  8C C0			        MOV     AX,ES                   ; Get the segment of the GDT
 0477  E8 0545 R		        CALL    SREG_2_24BITS           ; Convert to a 24 bit offset
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Page     1-13
                                                            

 047A  8A D6			        MOV     DL,DH                   ; Save a copy of the hi byte
 047C  BB C100			        MOV     BX,GDT_LOC              ; Add on the offset of the GDT
 047F  E8 0554 R		        CALL    ADDOFF
				
				        DESCR_INIT  SEG, GDT_PTR, GDT_LEN, BX, DH, CPL0_DATA_ACCESS
 0482  50                    1	        PUSH    AX            ; Save the utility register 
 0483  BF 0008               1	        MOV     DI,GDT_PTR     ; Set up index value to proper descriptor 
 0486  81 C7 C100            1	        ADD     DI,GDT_LOC 
 048A  B8 1000               1	        MOV     AX,GDT_LEN       ; PARM1 = Segment Limit; load into AX 
 048D  AB                    1	        STOSW                   ;   and store 
 048E  8B C3                 1	        MOV     AX,BX       ; PARM2 = BASE_LO_W; load into AX 
 0490  AB                    1	        STOSW                   ;   and store 
 0491  8A C6                 1	        MOV     AL,DH       ; PARM3 = BASE_HI_B; load into AL, and 
 0493  B4 93                 1	        MOV     AH,CPL0_DATA_ACCESS         ;   ARB = Access Rights Byte; load into AH 
 0495  AB                    1	        STOSW                   ;     and store both 
 0496  B8 0000               1	        MOV     AX,0            ; Make sure the Intel 
 0499  AB                    1	        STOSW                   ;   reserved word is zero 
 049A  58                    1	        POP     AX              ; Restore AX 
				
				; Initialize the descriptor for the IDT
				
 049B  BB D100			        MOV     BX,SIDT_LOC             ; DH,AX already contains the segment
				                                        ;   converted to 24 bits so all we
 049E  E8 0554 R		        CALL    ADDOFF                  ;   have to do is add on the offset
				
				        DESCR_INIT  SEG, MON_IDT_PTR, SIDT_LEN, BX, DH, CPL0_DATA_ACCESS
 04A1  50                    1	        PUSH    AX            ; Save the utility register 
 04A2  BF 0010               1	        MOV     DI,MON_IDT_PTR     ; Set up index value to proper descriptor 
 04A5  81 C7 C100            1	        ADD     DI,GDT_LOC 
 04A9  B8 0800               1	        MOV     AX,SIDT_LEN       ; PARM1 = Segment Limit; load into AX 
 04AC  AB                    1	        STOSW                   ;   and store 
 04AD  8B C3                 1	        MOV     AX,BX       ; PARM2 = BASE_LO_W; load into AX 
 04AF  AB                    1	        STOSW                   ;   and store 
 04B0  8A C6                 1	        MOV     AL,DH       ; PARM3 = BASE_HI_B; load into AL, and 
 04B2  B4 93                 1	        MOV     AH,CPL0_DATA_ACCESS         ;   ARB = Access Rights Byte; load into AH 
 04B4  AB                    1	        STOSW                   ;     and store both 
 04B5  B8 0000               1	        MOV     AX,0            ; Make sure the Intel 
 04B8  AB                    1	        STOSW                   ;   reserved word is zero 
 04B9  58                    1	        POP     AX              ; Restore AX 
				
				; Initialize the descriptor that accesses all of memory as data
				
				        DESCR_INIT  BSEG, HUGE_PTR, 0FFFFH, 0, 0, CPL0_DATA_ACCESS
 04BA  50                    1	        PUSH    AX            ; Save the utility register 
 04BB  BF 0020               1	        MOV     DI,HUGE_PTR     ; Set up index value to proper descriptor 
 04BE  81 C7 C100            1	        ADD     DI,GDT_LOC 
 04C2  B8 FFFF               1	        MOV     AX,0FFFFH       ; PARM1 = Segment Limit; load into AX 
 04C5  AB                    1	        STOSW                   ;   and store 
 04C6  B8 0000               1	        MOV     AX,0       ; PARM2 = BASE_LO_W; load into AX 
 04C9  AB                    1	        STOSW                   ;   and store 
 04CA  B0 00                 1	        MOV     AL,0       ; PARM3 = BASE_HI_B; load into AL, and 
 04CC  B4 93                 1	        MOV     AH,CPL0_DATA_ACCESS         ;   ARB = Access Rights Byte; load into AH 
 04CE  AB                    1	        STOSW                   ;     and store both 
 04CF  B8 0080               1	        MOV     AX,0080H        ; 4k granularity bit 
 04D2  AB                    1	        STOSW 
 04D3  58                    1	        POP     AX              ; Restore AX 
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Page     1-14
                                                            

				
				; Initialize the descriptors for the V86 task's LDT
				
 04D4  BB D900			        MOV     BX,DISPATCH_LOC                                           ; @P3C
 04D7  E8 0554 R		        CALL    ADDOFF
				
				        DESCR_INIT  SEG,SCRUBBER.VM_LDTR,00FFFH,BX,DH,LDT_DESC
 04DA  50                    1	        PUSH    AX            ; Save the utility register 
 04DB  BF 0FF0               1	        MOV     DI,SCRUBBER.VM_LDTR     ; Set up index value to proper descriptor 
 04DE  81 C7 C100            1	        ADD     DI,GDT_LOC 
 04E2  B8 0FFF               1	        MOV     AX,00FFFH       ; PARM1 = Segment Limit; load into AX 
 04E5  AB                    1	        STOSW                   ;   and store 
 04E6  8B C3                 1	        MOV     AX,BX       ; PARM2 = BASE_LO_W; load into AX 
 04E8  AB                    1	        STOSW                   ;   and store 
 04E9  8A C6                 1	        MOV     AL,DH       ; PARM3 = BASE_HI_B; load into AL, and 
 04EB  B4 E2                 1	        MOV     AH,LDT_DESC         ;   ARB = Access Rights Byte; load into AH 
 04ED  AB                    1	        STOSW                   ;     and store both 
 04EE  B8 0000               1	        MOV     AX,0            ; Make sure the Intel 
 04F1  AB                    1	        STOSW                   ;   reserved word is zero 
 04F2  58                    1	        POP     AX              ; Restore AX 
				        DESCR_INIT  SEG,SCRUBBER.LDT_PTR,00FFFH,BX,DH,CPL0_DATA_ACCESS
 04F3  50                    1	        PUSH    AX            ; Save the utility register 
 04F4  BF 0FF8               1	        MOV     DI,SCRUBBER.LDT_PTR     ; Set up index value to proper descriptor 
 04F7  81 C7 C100            1	        ADD     DI,GDT_LOC 
 04FB  B8 0FFF               1	        MOV     AX,00FFFH       ; PARM1 = Segment Limit; load into AX 
 04FE  AB                    1	        STOSW                   ;   and store 
 04FF  8B C3                 1	        MOV     AX,BX       ; PARM2 = BASE_LO_W; load into AX 
 0501  AB                    1	        STOSW                   ;   and store 
 0502  8A C6                 1	        MOV     AL,DH       ; PARM3 = BASE_HI_B; load into AL, and 
 0504  B4 93                 1	        MOV     AH,CPL0_DATA_ACCESS         ;   ARB = Access Rights Byte; load into AH 
 0506  AB                    1	        STOSW                   ;     and store both 
 0507  B8 0000               1	        MOV     AX,0            ; Make sure the Intel 
 050A  AB                    1	        STOSW                   ;   reserved word is zero 
 050B  58                    1	        POP     AX              ; Restore AX 
				
				; Initialize the descriptors for the V86 task's TR
				
 050C  BB D900			        MOV     BX,DISPATCH_LOC                                           ; @P3C
 050F  E8 0554 R		        CALL    ADDOFF
				
				        DESCR_INIT  SEG,SCRUBBER.VM_TR,TSS_LEN,BX,DH,FREE_TSS_386         ; @P3C
 0512  50                    1	        PUSH    AX            ; Save the utility register 
 0513  BF 0FE0               1	        MOV     DI,SCRUBBER.VM_TR     ; Set up index value to proper descriptor 
 0516  81 C7 C100            1	        ADD     DI,GDT_LOC 
 051A  B8 2068               1	        MOV     AX,TSS_LEN       ; PARM1 = Segment Limit; load into AX 
 051D  AB                    1	        STOSW                   ;   and store 
 051E  8B C3                 1	        MOV     AX,BX       ; PARM2 = BASE_LO_W; load into AX 
 0520  AB                    1	        STOSW                   ;   and store 
 0521  8A C6                 1	        MOV     AL,DH       ; PARM3 = BASE_HI_B; load into AL, and 
 0523  B4 89                 1	        MOV     AH,FREE_TSS_386         ;   ARB = Access Rights Byte; load into AH 
 0525  AB                    1	        STOSW                   ;     and store both 
 0526  B8 0000               1	        MOV     AX,0            ; Make sure the Intel 
 0529  AB                    1	        STOSW                   ;   reserved word is zero 
 052A  58                    1	        POP     AX              ; Restore AX 
				        DESCR_INIT  SEG,SCRUBBER.TSS_PTR,TSS_LEN,BX,DH,CPL0_DATA_ACCESS; @P3C
 052B  50                    1	        PUSH    AX            ; Save the utility register 
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Page     1-15
                                                            

 052C  BF 0FE8               1	        MOV     DI,SCRUBBER.TSS_PTR     ; Set up index value to proper descriptor 
 052F  81 C7 C100            1	        ADD     DI,GDT_LOC 
 0533  B8 2068               1	        MOV     AX,TSS_LEN       ; PARM1 = Segment Limit; load into AX 
 0536  AB                    1	        STOSW                   ;   and store 
 0537  8B C3                 1	        MOV     AX,BX       ; PARM2 = BASE_LO_W; load into AX 
 0539  AB                    1	        STOSW                   ;   and store 
 053A  8A C6                 1	        MOV     AL,DH       ; PARM3 = BASE_HI_B; load into AL, and 
 053C  B4 93                 1	        MOV     AH,CPL0_DATA_ACCESS         ;   ARB = Access Rights Byte; load into AH 
 053E  AB                    1	        STOSW                   ;     and store both 
 053F  B8 0000               1	        MOV     AX,0            ; Make sure the Intel 
 0542  AB                    1	        STOSW                   ;   reserved word is zero 
 0543  58                    1	        POP     AX              ; Restore AX 
				
 0544  C3			        RET
				
 0545				GDT_BLD         ENDP
				
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Page     1-16
                                                            

				PAGE
				; SREG_2_24BITS converts the segment register 16 bit value in the AX register
				; into a 24 bit value in DH and AX
				;
				;       Input :    AX = segment register value
				;
				;       Output:    AX = 24 bit low word
				;                  DH = 24 bit high byte
				
				
 0545				SREG_2_24BITS PROC    NEAR
				
				; Put the high four bits of AH into the low four bits of DH
				
 0545  8A F4			        MOV     DH,AH                   ; Get the high byte of the segment value
				                                        ;   into DH
 0547  80 E6 F0			        AND     DH,0F0H                 ; Strip off the low nibble
 054A  C0 EE 04			        SHR     DH,4                    ; Shift right four bits
				
				; Now shift AX left four bits
				
 054D  80 E4 0F			        AND     AH,00FH                 ; Strip high nibble from AH
				                                        ;   This keeps the carry flag from being
				                                        ;   set which could effect later ADDs.
 0550  C1 E0 04			        SHL     AX,4                    ; Shift AX
				
 0553  C3			        RET
				
 0554				SREG_2_24BITS ENDP
				
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Page     1-17
                                                            

				PAGE
				; ADDOFF adds the 16 bit offset in BX to the 24 bit value in DL and AX.  The
				; result is left in DH and BX.
				;
				;       Input :    DL = 24 bit high byte
				;                  AX = 24 bit low word
				;                  BX = offset to be added
				;
				;       Output:    DH = 24 bit high byte
				;                  BX = 24 bit low word
				
 0554				ADDOFF  PROC    NEAR
				
 0554  8A F2			        MOV     DH,DL                   ; Restore the high byte that was saved
				                                        ;   in DL
 0556  03 D8			        ADD     BX,AX                   ; Add on the offset
 0558  80 D6 00			        ADC     DH,0                    ; Add the carry, if any, to the high
				                                        ;   byte
 055B  C3			        RET
				
 055C				ADDOFF  ENDP
				
 055C				PROG    ENDS
				
				        END

Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Symbols-1


Macros:

		N a m e			Lines

DESCR_DEF  . . . . . . . . . . .  	  21
DESCR_INIT . . . . . . . . . . .  	  48

Structures and Records:

                N a m e                 Width   # fields
                                        Shift   Width   Mask    Initial

BPSTACK  . . . . . . . . . . . .  	0050	0028
  BP_ES  . . . . . . . . . . . .  	0000
  BP_DI  . . . . . . . . . . . .  	0002
  BP_SI  . . . . . . . . . . . .  	0006
  BP_BP  . . . . . . . . . . . .  	000A
  BP_PASP  . . . . . . . . . . .  	000E
  BP_PSP2  . . . . . . . . . . .  	0010
  BP_BX  . . . . . . . . . . . .  	0012
  BP_DX  . . . . . . . . . . . .  	0016
  BP_CX  . . . . . . . . . . . .  	001A
  BP_AX  . . . . . . . . . . . .  	001E
  BP_DS  . . . . . . . . . . . .  	0022
  BP_EX  . . . . . . . . . . . .  	0024
  BP_EC  . . . . . . . . . . . .  	0026
  BP_IP  . . . . . . . . . . . .  	002A
  BP_IP2 . . . . . . . . . . . .  	002C
  BP_CS  . . . . . . . . . . . .  	002E
  BP_CS2 . . . . . . . . . . . .  	0030
  BP_FL  . . . . . . . . . . . .  	0032
  BP_FL2 . . . . . . . . . . . .  	0034
  BP_SP  . . . . . . . . . . . .  	0036
  BP_SP2 . . . . . . . . . . . .  	0038
  BP_SS  . . . . . . . . . . . .  	003A
  BP_SS2 . . . . . . . . . . . .  	003C
  BP_VMES  . . . . . . . . . . .  	003E
  BP_VME2  . . . . . . . . . . .  	0040
  BP_VMDS  . . . . . . . . . . .  	0042
  BP_VMFS  . . . . . . . . . . .  	0046
  BP_VMGS  . . . . . . . . . . .  	004A
  BP_STK . . . . . . . . . . . .  	004E
CODE_ACC . . . . . . . . . . . .  	0008	0004
  DATA_HI  . . . . . . . . . . .  	0003	0005	00F8	0000
  CONFORM  . . . . . . . . . . .  	0002	0001	0004	0000
  READABLE . . . . . . . . . . .  	0001	0001	0002	0000
  DATA_LO  . . . . . . . . . . .  	0000	0001	0001	0000
DATA_ACC . . . . . . . . . . . .  	0008	0007
  PRESENT  . . . . . . . . . . .  	0007	0001	0080	0000
  DPL  . . . . . . . . . . . . .  	0005	0002	0060	0000
  SEG_TYPE . . . . . . . . . . .  	0004	0001	0010	0000
  XQTBLE . . . . . . . . . . . .  	0003	0001	0008	0000
  EXPDIR . . . . . . . . . . . .  	0002	0001	0004	0000
  WRTBLE . . . . . . . . . . . .  	0001	0001	0002	0000
  ACCESSED . . . . . . . . . . .  	0000	0001	0001	0000
DATA_DESC  . . . . . . . . . . .  	0008	0005
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Symbols-2


  SEG_LIMIT  . . . . . . . . . .  	0000
  BASE_LO_WORD . . . . . . . . .  	0002
  BASE_HI_BYTE . . . . . . . . .  	0004
  DATA_ACC_RIGHTS  . . . . . . .  	0005
  DATA_RESERVED  . . . . . . . .  	0006
GATE_DESC  . . . . . . . . . . .  	0008	0005
  ENTRY_POINT  . . . . . . . . .  	0000
  CS_SELECTOR  . . . . . . . . .  	0002
  WORD_COUNT . . . . . . . . . .  	0004
  GATE_ACC_RIGHTS  . . . . . . .  	0005
  GATE_RESERVED  . . . . . . . .  	0006
GDT_DEF  . . . . . . . . . . . .  	1001	0036
  UNUSED_ENTRY . . . . . . . . .  	0000
  GDT_PTR  . . . . . . . . . . .  	0008
  MON_IDT_PTR  . . . . . . . . .  	0010
  RSDA_PTR . . . . . . . . . . .  	0018
  HUGE_PTR . . . . . . . . . . .  	0020
  LA_PTR . . . . . . . . . . . .  	0028
  C_BWCRT_PTR  . . . . . . . . .  	0030
  C_CCRT_PTR . . . . . . . . . .  	0038
  E_CCRT_PTR . . . . . . . . . .  	0040
  E_CCRT_PTR2  . . . . . . . . .  	0048
  SYS_ROM_CS . . . . . . . . . .  	0050
  SYS_ROM_DS . . . . . . . . . .  	0058
  SYS_PATCH_CS . . . . . . . . .  	0060
  SYS_PATCH_DS . . . . . . . . .  	0068
  V_ROM_CS . . . . . . . . . . .  	0070
  V_ROM_DS . . . . . . . . . . .  	0078
  V_PATCH_CS . . . . . . . . . .  	0080
  V_PATCH_DS . . . . . . . . . .  	0088
  ES_TEMP  . . . . . . . . . . .  	0090
  CS_TEMP  . . . . . . . . . . .  	0098
  SS_TEMP  . . . . . . . . . . .  	00A0
  DS_TEMP  . . . . . . . . . . .  	00A8
  MON_LDTR . . . . . . . . . . .  	00B0
  MON_DS . . . . . . . . . . . .  	00B8
  MON_ES . . . . . . . . . . . .  	00C0
  MON_SS . . . . . . . . . . . .  	00C8
  MON_CS . . . . . . . . . . . .  	00D0
  MON_TR_SS  . . . . . . . . . .  	00D8
  MON_TR_BP  . . . . . . . . . .  	00E0
  MON_TR_HWI . . . . . . . . . .  	00E8
  MON_TR_OI  . . . . . . . . . .  	00F0
  KBD_OWNER_SDA  . . . . . . . .  	00F8
  VTIMER_VECTOR  . . . . . . . .  	0100
  SEX_TSS  . . . . . . . . . . .  	0180
  HWI_TSS  . . . . . . . . . . .  	0280
  DISPATCH_TASK  . . . . . . . .  	0380
  HWI_LDT  . . . . . . . . . . .  	0390
  BASICS_SEG . . . . . . . . . .  	0398
  BIOSS_SEG  . . . . . . . . . .  	03A0
  RSVD_GDT . . . . . . . . . . .  	03A8
  PM_VM  . . . . . . . . . . . .  	0DC0
  USER_CS  . . . . . . . . . . .  	0DE0
  USER_SS  . . . . . . . . . . .  	0DE8
  USER_DS  . . . . . . . . . . .  	0DF0
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Symbols-3


  USER_ES  . . . . . . . . . . .  	0DF8
  USER_TSS . . . . . . . . . . .  	0E00
  USER_TSS_DAT . . . . . . . . .  	0E08
  USER_LDT . . . . . . . . . . .  	0E10
  USER_LDT_DAT . . . . . . . . .  	0E18
  USER_VMS . . . . . . . . . . .  	0E20
  SCRUBBER . . . . . . . . . . .  	0FE0
  LAST_GDT_BYTE  . . . . . . . .  	1000
SELECTOR . . . . . . . . . . . .  	0010	0003
  INDEX  . . . . . . . . . . . .  	0003	000D	FFF8	0000
  TI . . . . . . . . . . . . . .  	0002	0001	0004	0000
  RPL  . . . . . . . . . . . . .  	0000	0002	0003	0000
SYSTEM_ACC . . . . . . . . . . .  	0008	0002
  DATA_H . . . . . . . . . . . .  	0004	0004	00F0	0000
  DESC_TYPE  . . . . . . . . . .  	0000	0004	000F	0000
TASK_STATE_286 . . . . . . . . .  	002C	0016
  BACK_LINK  . . . . . . . . . .  	0000
  VM_SP0 . . . . . . . . . . . .  	0002
  VM_SS0 . . . . . . . . . . . .  	0004
  VM_SP1 . . . . . . . . . . . .  	0006
  VM_SS1 . . . . . . . . . . . .  	0008
  VM_SP2 . . . . . . . . . . . .  	000A
  VM_SS2 . . . . . . . . . . . .  	000C
  VM_IP  . . . . . . . . . . . .  	000E
  VM_FL  . . . . . . . . . . . .  	0010
  VM_AX  . . . . . . . . . . . .  	0012
  VM_CX  . . . . . . . . . . . .  	0014
  VM_DX  . . . . . . . . . . . .  	0016
  VM_BX  . . . . . . . . . . . .  	0018
  VM_SP  . . . . . . . . . . . .  	001A
  VM_BP  . . . . . . . . . . . .  	001C
  VM_SI  . . . . . . . . . . . .  	001E
  VM_DI  . . . . . . . . . . . .  	0020
  VM_ES  . . . . . . . . . . . .  	0022
  VM_CS  . . . . . . . . . . . .  	0024
  VM_SS  . . . . . . . . . . . .  	0026
  VM_DS  . . . . . . . . . . . .  	0028
  VM_LDT . . . . . . . . . . . .  	002A
TSS386 . . . . . . . . . . . . .  	006C	002B
  ETSS_BACK_LINK . . . . . . . .  	0002
  ETSS_SP0 . . . . . . . . . . .  	0004
  ETSS_SS0 . . . . . . . . . . .  	0008
  ETSS_SP1 . . . . . . . . . . .  	000C
  ETSS_SS1 . . . . . . . . . . .  	0010
  ETSS_SP2 . . . . . . . . . . .  	0014
  ETSS_SS2 . . . . . . . . . . .  	0018
  ETSS_CR3 . . . . . . . . . . .  	001C
  ETSS_IP  . . . . . . . . . . .  	0020
  ETSS_FL  . . . . . . . . . . .  	0024
  ETSS_FL2 . . . . . . . . . . .  	0026
  ETSS_AX  . . . . . . . . . . .  	0028
  ETSS_CX  . . . . . . . . . . .  	002C
  ETSS_DX  . . . . . . . . . . .  	0030
  ETSS_BX  . . . . . . . . . . .  	0034
  ETSS_SP  . . . . . . . . . . .  	0038
  ETSS_BP  . . . . . . . . . . .  	003C
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Symbols-4


  ETSS_SI  . . . . . . . . . . .  	0040
  ETSS_DI  . . . . . . . . . . .  	0044
  ETSS_ES  . . . . . . . . . . .  	0048
  ETSS_CS  . . . . . . . . . . .  	004C
  ETSS_SS  . . . . . . . . . . .  	0050
  ETSS_DS  . . . . . . . . . . .  	0054
  ETSS_FS  . . . . . . . . . . .  	0058
  ETSS_GS  . . . . . . . . . . .  	005C
  ETSS_LDT . . . . . . . . . . .  	0060
  ETSS_TRAP  . . . . . . . . . .  	0064
  ETSS_BM_OFFSET . . . . . . . .  	0066
  ETSS_AVL . . . . . . . . . . .  	0068
VM_GDT_ENTRY . . . . . . . . . .  	0020	0004
  VM_TR  . . . . . . . . . . . .  	0000
  TSS_PTR  . . . . . . . . . . .  	0008
  VM_LDTR  . . . . . . . . . . .  	0010
  LDT_PTR  . . . . . . . . . . .  	0018

Segments and Groups:

                N a m e         	Length	 Align	Combine Class

PROG . . . . . . . . . . . . . .  	055C	PARA	PUBLIC	'PROG'

Symbols:            

                N a m e         	Type	 Value	 Attr

ACCESSED . . . . . . . . . . . .  		0000	
ADDOFF . . . . . . . . . . . . .  	N PROC	0554	PROG	Length = 0008
ALLSET . . . . . . . . . . . . .  	L NEAR	0443	PROG

BOOT_CS  . . . . . . . . . . . .  	NUMBER	0000	
BOOT_FL  . . . . . . . . . . . .  	NUMBER	0200	
BOOT_IP  . . . . . . . . . . . .  	NUMBER	7C00	
BOOT_SP  . . . . . . . . . . . .  	NUMBER	07FF	
BOOT_SS  . . . . . . . . . . . .  	NUMBER	0030	
BP_START . . . . . . . . . . . .  	NUMBER	0000	
BUSY_TSS . . . . . . . . . . . .  	NUMBER	0083	

CALL_GATE  . . . . . . . . . . .  	NUMBER	0084	
CARD_ENABL . . . . . . . . . . .  	NUMBER	0004	
CCRT@_HI . . . . . . . . . . . .  	NUMBER	000B	
CCRT@_LO . . . . . . . . . . . .  	NUMBER	8000	
CCRT_SIZE  . . . . . . . . . . .  	NUMBER	4000	
COMP_CODE_ACCESS . . . . . . . .  	ALIAS	 CPL3_DATA_ACCESS		
CONFORM  . . . . . . . . . . . .  		0002	
COPY_LEN . . . . . . . . . . . .  	NUMBER	0430	
CPL0_CODE_ACCESS . . . . . . . .  	NUMBER	009B	
CPL0_DATA_ACCESS . . . . . . . .  	NUMBER	0093	
CPL3_CODE_ACCESS . . . . . . . .  	NUMBER	009F	
CPL3_DATA_ACCESS . . . . . . . .  	NUMBER	00F3	
CSEG@_HI . . . . . . . . . . . .  	NUMBER	000E	
CSEG@_LO . . . . . . . . . . . .  	NUMBER	0000	
CS_HI_CACHE  . . . . . . . . . .  	NUMBER	0000	
CS_LO_CACHE  . . . . . . . . . .  	NUMBER	0000	
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Symbols-5



DATA_H . . . . . . . . . . . . .  		0004	
DATA_HI  . . . . . . . . . . . .  		0003	
DATA_LO  . . . . . . . . . . . .  		0000	
DESC_LEN . . . . . . . . . . . .  	NUMBER	0008	
DESC_TYPE  . . . . . . . . . . .  		0000	
DESC_WIDTH . . . . . . . . . . .  	NUMBER	0003	
DISPATCH_LOC . . . . . . . . . .  	NUMBER	D900	
DPL  . . . . . . . . . . . . . .  		0005	
DPL0 . . . . . . . . . . . . . .  	NUMBER	0000	
DPL1 . . . . . . . . . . . . . .  	NUMBER	0020	
DPL2 . . . . . . . . . . . . . .  	NUMBER	0040	
DPL3 . . . . . . . . . . . . . .  	NUMBER	0060	

ECCRT@_HI_HI . . . . . . . . . .  	NUMBER	000C	
ECCRT@_HI_LO . . . . . . . . . .  	NUMBER	0000	
ECCRT@_LO_HI . . . . . . . . . .  	NUMBER	000A	
ECCRT@_LO_LO . . . . . . . . . .  	NUMBER	0000	
ECCRT_SIZE . . . . . . . . . . .  	NUMBER	FFFF	
EXPDIR . . . . . . . . . . . . .  		0002	

FREE_TSS . . . . . . . . . . . .  	NUMBER	0081	
FREE_TSS_386 . . . . . . . . . .  	NUMBER	0089	

GATE_ACCESS  . . . . . . . . . .  	NUMBER	0080	
GDT_BLD  . . . . . . . . . . . .  	N PROC	0430	PROG	Global	Length = 0115
GDT_DATA_END . . . . . . . . . .  	L WORD	0430	PROG
GDT_DATA_START . . . . . . . . .  	L WORD	0000	PROG	Global
GDT_LEN  . . . . . . . . . . . .  	NUMBER	1000	
GDT_LOC  . . . . . . . . . . . .  	NUMBER	C100	
GO_MODE  . . . . . . . . . . . .  	NUMBER	0001	

INDEGDT  . . . . . . . . . . . .  	L NEAR	0000	PROG	Global
INDEX  . . . . . . . . . . . . .  		0003	
INT_GATE . . . . . . . . . . . .  	NUMBER	0086	

LA_LEN . . . . . . . . . . . . .  	ALIAS	 GDT_LEN		
LDT_ACCESS . . . . . . . . . . .  	NUMBER	00E0	
LDT_DESC . . . . . . . . . . . .  	NUMBER	00E2	
LDT_LEN  . . . . . . . . . . . .  	NUMBER	0800	

MAX_SEG_LEN  . . . . . . . . . .  	NUMBER	FFFF	
MCRT@_HI . . . . . . . . . . . .  	NUMBER	000B	
MCRT@_LO . . . . . . . . . . . .  	NUMBER	0000	
MCRT_SIZE  . . . . . . . . . . .  	NUMBER	1000	
MEMX . . . . . . . . . . . . . .  	NUMBER	0002	
MSEG@_HI . . . . . . . . . . . .  	NUMBER	0008	
MSEG@_LO . . . . . . . . . . . .  	NUMBER	0000	

NEXT_DESC  . . . . . . . . . . .  	NUMBER	0008	
NSEG@_HI . . . . . . . . . . . .  	NUMBER	0000	
NSEG@_LO . . . . . . . . . . . .  	NUMBER	0000	
NULL_ACCESS  . . . . . . . . . .  	NUMBER	0000	
NULL_SEG_LEN . . . . . . . . . .  	NUMBER	0000	

OTHER_CACHE  . . . . . . . . . .  	NUMBER	0000	
Microsoft (R) Macro Assembler Version 5.10                  5/17/24 09:44:11
INDEGDT - 386 XMA Emulator - Build Global Descriptor Table  Symbols-6



PM_VM_SIZE . . . . . . . . . . .  	NUMBER	1000	
PRESENT  . . . . . . . . . . . .  		0007	

READABLE . . . . . . . . . . . .  		0001	
RPL  . . . . . . . . . . . . . .  		0000	

SEG_TYPE . . . . . . . . . . . .  		0004	
SHADOW_ID  . . . . . . . . . . .  	ALIAS	 DATA_RESERVED		
SIDT_LEN . . . . . . . . . . . .  	NUMBER	0800	
SIDT_LOC . . . . . . . . . . . .  	NUMBER	D100	
SREG_2_24BITS  . . . . . . . . .  	N PROC	0545	PROG	Global	Length = 000F
SS_HI_CACHE  . . . . . . . . . .  	NUMBER	0000	
SS_LO_CACHE  . . . . . . . . . .  	NUMBER	0300	
S_MODE . . . . . . . . . . . . .  	NUMBER	2000	

TASK_GATE  . . . . . . . . . . .  	NUMBER	0085	
THIRTY_TWO_K . . . . . . . . . .  	NUMBER	8000	
TI . . . . . . . . . . . . . . .  		0002	
TRAP_GATE  . . . . . . . . . . .  	NUMBER	0087	
TSS_386_LEN  . . . . . . . . . .  	NUMBER	0068	
TSS_ACCESS . . . . . . . . . . .  	NUMBER	0080	
TSS_BM_LEN . . . . . . . . . . .  	NUMBER	0F97	
TSS_LEN  . . . . . . . . . . . .  	NUMBER	2068	

VIRTUAL_ENABLE . . . . . . . . .  	NUMBER	0001	
VM_ENTRY_LENGTH  . . . . . . . .  	NUMBER	0020	
VM_ENTRY_WIDTH . . . . . . . . .  	NUMBER	0005	

WRTBLE . . . . . . . . . . . . .  		0001	

XQTBLE . . . . . . . . . . . . .  		0003	

@CPU . . . . . . . . . . . . . .  	TEXT  1415		
@FILENAME  . . . . . . . . . . .  	TEXT  INDEGDT		
@VERSION . . . . . . . . . . . .  	TEXT  510		


   1132 Source  Lines
   2279 Total   Lines
    263 Symbols

  46280 + 177977 Bytes symbol space free

      0 Warning Errors
      0 Severe  Errors
